Research
A few threads I've been pulling on…
FlexPosit
Precision as a continuously tunable hardware resource
Mixed-precision quantization gives you rich tradeoffs in software, then wrecks the regular dataflow accelerators depend on. FlexPosit gets both.
- posit arithmetic
- LLM inference
- mixed-precision quantization
- bit-serial systolic array
EdgeScope
Design space exploration that puts the host CPU inside the design space
Existing DSE tools model the accelerator in isolation. Spend your area budget on that advice and you can buy a bigger array for a workload that was never compute-bound.
- NPU
- MLIR / IREE
- compiler and runtime
- design space exploration
- host bottleneck
Edge-MPQ
Mixed-precision inference units built into a RISC-V pipeline, and a search that knows what the hardware can do
Layer-wise mixed precision beats uniform quantization — but the search has to know what the hardware supports, and the hardware has to actually support it.
- mixed-precision quantization
- RISC-V
- ISA co-design
- INT2–INT8
- 14nm
LiteAIR5
An AI-extended RISC-V core, and the end-to-end framework to design one
Traditional edge AI hardware either isn't fast enough or costs too much power and area. A third option needs tooling that sees the whole system.
- RISC-V
- ISA extensions
- SoC generation
- FPGA emulation
- edge AI
CryptoPUF
A weak PUF and a crypto core, each covering the other's weakness
Strong PUFs fall to machine learning. Crypto cores resist ML but have no intrinsic key. Put them together and each one's weakness is the other's strength.
- hardware security
- PUF
- ML-resilient
- IoT
- RFID
Membrane
Bit-serial comparison inside DRAM, so most rows never leave memory
Analytical queries read enormous amounts of data and discard most of it. Better to discard it before it crosses the bus.
- processing-in-memory
- DRAM
- bit-serial
- database analytics